document number: 63225 www.vishay.com s11-1274-rev. a, 04-jul-11 1 this document is subject to change without notice. the products described herein and this document are subject to specific disclaimers, set forth at www.vishay.com/doc?91000 p-channel 8 v (d-s) mosfet spice device model SI2329DS vishay siliconix description the attached spice model desc ribes the typical electrical characteristics of the p-channel vertical dmos. the subcircuit model is extracted and optimized over the - 55 c to + 125 c temperature ranges under the pulsed 0 v to 5 v gate drive. the sa turated output impedanc e is best fit at the gate bias near the threshold voltage. a novel gate-to-drain feedback capacitance network is used to model the gate charge characteristics while avoiding convergence difficulties of the switched c gd model. all model parameter values are optimized to provide a best fit to the measured electrical data and are not intended as an exact physical interpretation of the device. characteristics ? p-channel vertical dmos ? macro model (subcircuit model) ?level 3 mos ? apply for both linear and switching application ? accurate over the - 55 c to + 125 c temperature range ? model the gate charge, transient, and diode reverse recovery characteristics subcircuit model schematic note ? this document is intended as a spice modeling guideline and do es not constitute a commercial product datasheet. designers shou ld refer to the appropriate datasheet of the same number for guaranteed specification limits. d s dbd c gs m 1 g 3 r 1 m 2 gx r g c gd gy etcv + C
www.vishay.com document number: 63225 2 s11-1274-rev. a, 04-jul-11 this document is subject to change without notice. the products described herein and this document ar e subject to specific disclaimers, set forth at www.vishay.com/doc?91000 spice device model SI2329DS vishay siliconix notes a. pulse test; pulse width ? 300 s, duty cycle ? 2 %. b. guaranteed by design, not su bject to production testing. specifications (t j = 25 c, unless otherwise noted) parameter symbol test conditions simulated data measured data unit static gate-source threshold voltage v gs(th) v ds = v gs , i d = - 250 a 0.5 - v drain-source on-state resistance a r ds(on) v gs = - 4.5 v, i d = - 5.3 a 0.024 0.025 ? v gs = - 2.5 v, i d = - 4.8 a 0.028 0.030 forward transconductance a g fs v ds = - 4 v, i d = - 5.3 a 19 20 s diode forward voltage v sd i s = - 4.2 a - 0.72 - 0.80 v dynamic b input capacitance c iss v ds = - 10 v, v gs = 0 v, f = 1 mhz 1480 1485 pf output capacitance c oss 481 480 reverse transfer capacitance c rss 438 435 total gate charge q g v ds = - 4 v, v gs = - 4.5 v, i d = - 5.3 a 17 19.3 nc v ds = - 4 v, v gs = - 2.5 v, i d = - 5.3 a 11 11.8 gate-source charge q gs 1.7 1.7 gate-drain charge q gd 6.2 6.2
document number: 63225 www.vishay.com s11-1274-rev. a, 04-jul-11 3 this document is subject to change without notice. the products described herein and this document are subject to specific disclaimers, set forth at www.vishay.com/doc?91000 spice device model SI2329DS vishay siliconix comparison of model with measured data (t j = 25 c, unless otherwise noted) note ? dots and squares represent measured data. i d - drain current (a) v d s - drain-to- s ource voltage (v ) i d - drain current (a) v gs - g ate-to- s ource voltage (v) i d - drain current (a) c - capacitance (pf) v d s - drain-to- s ource voltage (v) q g - total g ate charge (nc) v gs - g ate-to- s ource voltage (v) i s - s ource current (a) v s d - s ource-to-drain voltage (v) r d s (on) - on-re s i s tance ( ) 0 5 10 15 20 0.0 0.5 1.0 1.5 2.0 v gs = 1.5 v v gs = 1 v v gs = 5 v, 3 v, 2.5 v, 2 v 0 1 2 3 4 5 0.0 0.3 0.6 0.9 1.2 1.5 t j = 25 c t j = - 55 c t j = 125 c 0.015 0.030 0.045 0.060 0.075 0.090 0 5 10 15 20 v gs = 4.5 v v gs = 2.5 v 0 700 1400 2100 2800 02468 c i ss c o ss c r ss 0 1 2 3 4 5 0 5 10 15 20 v d s = 4 v i d = 5.3 a 0.1 1 10 00.20.40.60.81 t j = 150 c t j = 25 c
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